RISC-V Vector is roughly equivalent to MMX, SSE, and AVX. A lot of tasks without those instructions are flat out slower without.

A TL;DR doesn't explain everything. The Milk-V Titan doesn't have Vector instructions or crypto, while the Pi 5 does. It's very clearly a broken benchmark.

This is why a bunch of RISC-V people won't buy boards without RV Vector instructions.

It's a broken benchmark since the CPU's shortcomings affect the results..?

Something is odd here, the Core 2 Duo only has up to SSE 4.1, while the RVA23 instruction set is analogous to x64-v3. I find it hard to believe that the SpacemiT K3 matched a Core 2 duo single core score while leveraging those new instructions.

To wit the Geekbench 6.5.0 RISC-V preview has 3 files, 'geekbench6', 'geekbench_riscv64', and 'geekbench_rv64gcv', which are presumably the executables for the benchmark in addition to their supported instruction sets. This makes the score an unreliable narrator of performance, as someone could have run the other benchmarks and the posted score would not be genuine. And that's on top of a perennial remark that even the benchmark(s) could just not be optimized for RISC-V.

If it's anything like the k1, I wouldn't be surprised if Core 2 performance was on the table. The released specs are are ~Sandybridge-Haswell like, but those were architectures made by (at the time) the top CPU manufacturer and were carefully balanced architectures to maximize performance while minimizing transistors. SpaceMIT is playing on easy mode (they are making a chip on a ~2-4x smaller process node and aren't pioneering bleeding edge techniques), but balancing an out of order CPU is still tough, and it's totally possible to lose 50% of theoretical ipc if you don't have the memory bandwith, cache hierarchy, scheuling etc.

Cache issues add another layer here, if it's not the whole issue. Device tree patches for the K3 have 2 clusters of 4 cores with shared 4MB L2 cache per cluster. Core 2 Duo P8400 has 3MB L2 shared between 2 cores, and Sandybridge-Haswell have per core L2 and shared L3.

LoongArch is a weird mix of MIPS and RISC-V. There's not much that would be gained by investing a whole bunch into LoongArch that couldn't also be done to RISC-V, if at all.

LoongArch has the advantage that they don't need to rely on a committee, they can just do things as they see fit.

The 2023 3A6000 already reached the performance of this RISC-V board

Thing about RISC-V is that there are technically no barriers on doing as you see fit, but there's very clearly defined lines where community support isn't guaranteed, like custom extensions or screwing with already ratified extensions.

We actually don't know a lot about the UR-DP1000 chip, while we do know quite a bit about the 3A6000 because of Chips and Cheese. This makes a thorough analysis of the crimes committed within the core architecture of the UR chip more of speculation than a coherent discussion.

But we do know:

1. The UR-DP1000 does not have any Vector instructions 2. UR only has a 4 way OOO design, while the 3A6k is 6 way OOO 3. The cache architecture of the UR is more complicated, with 4 cores sharing 4MB L3 per cluster (2 clusters total), and a 16MB global L4 where the 3A6k doesn't have this 4. The UR chip doesn't have SMT

KWin/Xorg AFAIK has been on maintanence duty (i.e. fixes mostly come from XWayland) for >5 years now. KDE has expulsed the Xorg codebase of KWin into a seperate repo in preparation of a Wayland only future.

Even if KDE/Xorg is a stable experience is true now, it will not be true in the medium to short term. And a distro like Kubuntu might be 2 years out from merging a "perfect" KDE Plasma experience if it arrived right now.

My 2 cents is that Geely could leverage their existing Volvo and Polestar dealership network much like KIA/Hyundai. Geely Holdings own ~80% of Volvo cars, and a majority share of Polestar. Polestar doesn't own any manufacturing facilities, instead using Geely or Volvo factories.

Geely's entry into the US EV market could/should ultimately be downmarket of Volvo/Polestar, since both of those are luxury vehicle brands.

There's something to be said that mass production is another distinct stage of invention. Karl Benz may have invented the first internal combustion engine car, and plenty more built cars by hand for the rich, but Henry Ford made cars anyone could have for cheap.

I agree with that. It is a bit like the idea that having an idea for a startup is less important than the ability to get it to a level where investors might be interested.

A while ago there was an artical posted here about all the world changing inventions that came out of Bell Labs. It was easy to show for most of them that they weren't the actual inventor, and in many cases not even the first producer. They were the first to make it practical for mass production, however.

You may like this book called The Origins of Efficiency: https://press.stripe.com/origins-of-efficiency

Or the author's newsletter: https://www.construction-physics.com/

As Elon Musk said, the machine to make the machine is much harder to make.

$1M to the US Government is like dropping pennies, less than that actually. By the READMEs, this font is actually a modification to another font and more sleuthing revealed that the author actually worked on this in his spare time.

drop enough pennies here and there and it adds up

That's a comical amount of pennies

Part of making a typeface is making it subconsciously part of the brand. Though there's precedent for making a functional font in this use case as Airbus designed B612 for readability within their glass cockpits.

Maybe if the font wouldn't be so generic that could be true but it's... bland, and uninteresting. Could be replaced by 2 dozen other

> as Airbus designed B612 for readability within their glass cockpits.

weird it still has problem of O being similar to 0. I guess it's less of a problem in plane instruments but still

Considering that the support tier where you get access to the testing suite is 150K/year, I don't think they will be spilling any beans soon.