> Also I still haven’t figured out how to combine a mechanical and digital solution. Like I want light switches that match my server state for my lights. If I change the switch via my phone, I want the switches to change as well so that the physical switch is always the true state of the light.
For the lights that I want to "keep mechanically in sync" I replaced the switches with buttons and used a re-flashed (ESPhome) sonoff-mini which conveniently has a button input for the relay.
Everything is synchronized no matter the operating interface.
> The hardware industry can't benefit from rapid iteration because every iteration costs a mask set.
Before tapeout there are steps which could benefit I suppose. But as a functional-programming n00b I don't see how that could be the solution. I would argue that improving place and route algorithms to the point that deploying to a (large) FPGA is almost as quick as compiling software would be a huge step forward.
VHDL springs off of ADA, so I wouldn't say it was specifically developed.
Anyway, ADA and VHDL are strongly typed, which incidentally works well with critical applications development such as hardware design.
VHDL springs off of Ada (not an acronym, no need to shout or to bring in the Americans with Disabilities Act into a discussion on programming) syntax, but not its semantics (or, its not a continuation of Ada semantics, it does borrow some of them).
PL/SQL (I've never used it) also borrows from Ada's syntax, but not its semantics in any comprehensive sense. This sort of thing was deliberate, similar to how Verilog borrows from C's syntax, or Java apes C's syntax, or JavaScript apes Java's (and C, indirectly). The goal was to extend something familiar with new semantics.
You have high-level-synthesis tools on many FPGA vendors tools, using C/C++ or even Python for hardware description. I personally don't think they are superior than typical HDLs, the thing that makes the difference is to think about the circuit you ought to describe, the language you use then is not as important IMHO.
HDL (hardware description languages - Verilog and VHDL the most representative ones) do actually work like that.
They give you access to structural descriptions for bitwise control, but also and mostly behavioural descriptions which allows hierarchies of modules (the blocks you described) and abstraction up to anywhere basically. This last part is generally referred to as RTL (register transfer level) design.
To make a circuit from this RTL description you usually need more steps: synthesis (where RTL gets "compiled" into the actual gates and flops to be used) and implementation (where the logic gates of the previous step are actually translated in the "fabric" you have available - FPGA logic blocks, a foundry's standard cell library ...).
> One of the biggest problems with being indispensable and announcing that you feel stuck, is that the business will take steps to get you even more stuck, through more money, shinier titles and stock options.
This worries me, as I'm experiencing it right at this time. No idea how to get unstuck either.
