Vivado isn't just an IDE, it's a toolchain. Poor or buggy verilog support, synthesis bugs, etc. can definitely influence the choice of FPGA's. And FPGA toolchains are all very buggy. Current issues we have involve that Vivado cannot reproduce builds even with the same seed.
Our main reason to not have picked Altera was usually much poorer routing and inability to meet our bandwidth demands (>100Gb/s), but the poorer toolchain was also a factor.
However, for IDE, it can be a killer if use is a requirement.
Our main reason to not have picked Altera was usually much poorer routing and inability to meet our bandwidth demands (>100Gb/s), but the poorer toolchain was also a factor.
However, for IDE, it can be a killer if use is a requirement.