RISC-V is a mess of dozens of extensions vendors can decide to implement with the option of adding custom instruction as well. The application profiles are recommended sets of extensions to implement for certain use-cases e.g. microcontrollers without operating systems, embedded systems with full operating systems etc.
The base ISA is very minimal resulting in long inefficient code sequences for common GPU tasks. It would be tempting to implement the vector extension and see how well it maps to GPU workloads, but afaik nobody has done this in earnest. The more traditional way would be to implement lots of small cores and extend them with packed SIMD (at least 4x Int32+FP32).
I know a bit of AMD GPU machine code, and it seems based on what I heard that RISC-V has only support for 'GPU vector' instructions, not 'GPU scalar' instructions, namely no "hardware thread mask" definition.
And I heard that RISC-V GPU ISA was already extended with raytracing hardware instructions.
For sure, 3D pipeline programing will be specific to one implementation, but since vulkan/dx12, it would have to be hardware command ring buffers (like for AMD GPUs).
The base ISA is very minimal resulting in long inefficient code sequences for common GPU tasks. It would be tempting to implement the vector extension and see how well it maps to GPU workloads, but afaik nobody has done this in earnest. The more traditional way would be to implement lots of small cores and extend them with packed SIMD (at least 4x Int32+FP32).